This web site is being maintained by John R. Barnes, who was the President and Chief Engineer of dBi Corporation from 2002 to September 30, 2013, when we closed because ObamaCrap made it too expensive for us to remain in business.

John R. Barnes KS4GL, PE, NCE, NCT, ESDC Eng, ESDC Tech, PSE, Master EMC Design Engineer, SM IEEE
December 31, 2010


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[68] "Power Distribution on the PCB," Eldre.

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[73] "Thermal & Reliability Study on High Current Thermal Vias & Output Pins," Synqor Application Note 00-08-01. (download from

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[79] Beltz, Walter, personal communication, August 10, 1999.

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[84] Buetow, Mike, "Air and Space: Voltage Behavior Gets a New Look," PC Fab, vol. 23 no. 11, pp. 8-12, November 2000.

[85] Buetow, Mike, "Re: current vs trace width graphs," DesignerCouncil archive #1600, 17 SEP 1997. (download from

[86] Campbell, Larry. "Thermal relief not sufficient for current -Reply," DesignerCouncil archive #002810, 22 Jun 1998. (download from

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[89] Doeling, Wally, "Re: Design: vias: current carrying capability," TechNet archive #016140, 19 Dec 1997. (download from

[90] Ferrari, Gary, "Re: Re[2] - heavy copper...," DesignerCouncil archive, 18 Apr 1996. (download from

[91] Ferrari, Gary, "Re: DES: Current Through Vias," TechNet archive #003916, 25 Jun 1996. (download from

[92] Ffitch, Clive, "Re: DES: Current carrying capacity of innerlayer planes," TechNet archive #011117, 19 May 97. (download from

[93] Frank, Frank, "Re: thermal relief not sufficient for current," DesignerCouncil archives #002808, 19 June 1998. (download from

[94] Friar, Michael E., and McClurg, Roger H., "Printed Circuits and High Currents," Design News, vol. 23 no. 25, pp. 103-107, December 6, 1968.

[95] Gagnon, Gerald, "Re: Maximum FR4 operating temperature," TechNet archive #019748, 11 May 1998. (download from

[96] Gentchev, Angel, "Designing high-current VRM-compliant CPU power supplies," EDN, vol. no. 22, pp. 155-158, October 26, 2000.

[97] Gregory, Steve, "Re: Exacta Circuits," TechNet archive #000383, 11 Aug 1995. (download from

[98] Hersey, Ralph, "DES: RE>Sheet Resistivity of 1 OZ. Copper," TechNet archive #005858, 14 Oct 1996. (download from

[99] Hersey, Ralph, "FAB- E-Glass Vs S-Glass," TechNet archive #002111, 1 Mar 1996. (download from

[100] Hersey, Ralph, "FWD>DES/FAB - hole wall thic," TechNet archive #002519, 10 Apr 1996. (download from

[101] Hersey, Ralph, "FWD>more heavy copper...," TechNet archive #004116, 10 Jul 1996. (download from

[102] Hersey, Ralph, "FWD>RE>Conductor widths," TechNet archive #002533, 11 Apr 1996. (download from

[103] Hersey, Ralph, "Re: IPC spec IPC-A-600D," TechNet archive #001984, 21 Feb 1996. (download from

[104] Hersey, Ralph, "Re: Circuit width and spacing," TechNet archive #015122, 11 Nov 1997. (download from

[105] Hersey, Ralph, "Re: Current Capacity of vias," TechNet archive #024099, 4 Sep 1998. (download from

[106] Hersey, Ralph, "Re: current carrying capacity of vias," TechNet archive #019464, 1 May 1998. (download from

[107] Hersey, Ralph, "RE>DES>Current Carrying Capacity," TechNet archives #005871, 15 Oct 1996. (download from

[108] Hersey, Ralph, "Re: Design: vias:current carrying capacity," TechNet archive #016126, 19 Dec 1997. (download from

[109] Hersey, Ralph, "Re: RE>Ground Planes," TechNet archive #001813, 12 Feb 1996. (download from

[110] Hersey, Ralph, "Re: Thermals DERATING Curves," TechNet archive #010688, 25 Apr 1997. (download from

[111] Hersey, Ralph, "Re: Trace Widths for PCB's," TechNet archive #019791, 11 May 1998. (download from

[112] Hersey, Ralph, "Re>DES>Current Carrying Capacity," TechNet archive #5871, 15 Oct 1996. (download from

[113] Hinton, Phil, "Re: FAB: IPC-4101 vs Mil-S-13949," TechNet archive #018181, 13 Mar 1998. (download from

[114] Hurst, Joe, "Re: current carrying capacity of vias," TechNet archive #019461, 1 May 1998. (download from

[115] Hybiske, Tom, "Re: FR4 versus FR5," TechNet archive #000571, 07 Sep 1995. (download from

[116] Jennings, C. W., "Electrical Properties of Printed Wiring Boards," Sandia Labs SAND75-0663, May 1976.

[117] Jodoin, Claude J., "Designer's Viewpoint," Printed Circuit Design, vol. 14 no. 8, pp. 41-42, August 1997.

[117a] Jouppi, Michael R., and Mason, Robert, "Current-Carrying Capacity of PWB Internal Conductors in Space Environments," iTherm 2000 Seventh Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, Las Vegas, NV, May 23-26, 2000, pp. 255-263.

[118] Landis, Jim, "Shopping for High-Density PCBs," EP&P, vol. 40 no. 3, pp. 44-49, March 2000.

[119] Lewandowski, Bob, "Re: [SI-LIST]: Current flow limit for wire bonding," SI-List, October 4, 2000.

[119a] Ling, Yun, "On Current Carrying Capacities of PCB Traces," 2002 Proceedings 52nd Electronic Components & Technology Conference, San Diego, CA, May 28-31, 2002, pp. 1683-1693.

[120] Lomax, Abdulrahmam, "Re: Current Capacity of via holes," DesignerCouncil archive #003207, 15 Sep 1998. (download from

[121] Lux, Jim, "High Voltage Fuses," 1997. (download from

[122] Magee, Andrew P., "Heat Rise Calculations," TechNet archive #006727, 15 Nov 1996. (download from

[123] Magee, Andrew P., "Re: Copper Thickness Designation," TechNet archive #001556, 24 Jan 1996. (download from

[124] Magee, Andy, "Re: High Current PCB," Technet archive #026751, 13 Jan 1999. (download from

[125] Mander, David, "re: FR-4 vs FR-5," TechNet archive #000579, 08 Sep 1995. (download from

[126] Martocchi, Sandra, "Derating Too Conservative for Today's PWBs," Printed Circuit Design, vol. 17 no. 4, pp. 36, April 2000.

[126a] May, J. Thomas, Gordon, M. L., Piwnica, W. M., and Bray, S. B., "The DC Fusing Current and Safe Operating Current of Microelectronic Bonding Wires," International Symposium for Testing and Failure Analysis, Los Angeles, CA, Nov. 6-10, 1989, pp. 121-131.

[127] McHardy, John, and Gandhi, Mahendra, "Empirical Equation for Sizing Copper PWB Traces," IPCWorks 1997, technical paper SO6-2-1, 1997.

[128] McKean, Doug, "Re: Current Capacity of vias," TechNet archive #024104, 4 Sep 1998. (download from

[129] McKean, Doug, "Re: Design: vias: current carrying capacity," TechNet archive #016146, 19 Dec 1997. (download from

[130] McKean, Doug, "Re: Temperature Rise on a Trace," TechNet archive #026221, 15 Dec 1998. (download from

[131] McMaster, Mike, "RE: Specifying copper thickness," TechNet archive #031629, 25 Jun 1999. (download from

[132] Mei, Lum Wee, "Re: Current capacity of vias," TechNet archive #024102, 5 Sep 1998. (download from

[133] Mei, Lum Wee, "Re: [DC] max current for via's," DesignerCouncil archive #003085, 31 Aug 1998. (download from

[134] Olson, Jack, "Re: current vs trace width graphs," DesignerCouncil archive #1594, 15 Sep 1997. (download from

[135] Olson, Jack, "Re: heavy copper...," DesignerCouncil archive #500, 13 Apr 1996. (download from

[135a] Pan, Tsung-Yu, Poulson, Russell H., and Blair, Howard D., "Current Carrying Capacity of Copper Conductors in Printed Wiring Boards," 1993 Proceedings 43rd Electronic Components & Technology Conference, Orlando, FL, June 1-4, 1993, pp. 1061-1066.

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[137] Rainal, A. J., "Temperature Rise at a Constriction in a Current- Carrying Printed Conductor," Bell System Technical Journal, vol. 55 no. 2, pp. 233-268, February 1976.

[138] Ritchey, Lee W., "A Surbey and Tutorial of Dielectric Materials Used int the Manufacture of Printed Circuit Boards," Circuitree, November 1999.

[139] Seeger, Jeff, "Re: High Current PCB," TechNet archive #026771, 14 JAN 1999. (download from

[140] Sober, Doug, "Re: FR4 versus FR5," TechNet archive #000637, 14 Sep 1995. (download from

[141] Sober, Doug, "Re: Specifying copper thickness," TechNet archive #031634, 25 Jun 1999. (download from

[142] Stevenson, Craig, personal communication, July 13, 1999.

[142a] Suppanz, Brad, "PCB Trace Width Calculator," 1998. (download from

[143] Sugden, Mary, and Johnson, Mona, "Conductor Width - Part 1," Printed Circuit Design, vol. 14 no. 10, pp. 38-39, October 1997.

[144] Sugden, Mary, and Johnson, Mona, "Holes - Part 1," Printed Circuit Design, vol. 14 no. 5, pp. 34-35, May 1997.

[145] Weick, Walter W., "Measuring Printed Circuits' Current-Carrying Capacity," Western Electric Engineer, vol. 5, pp. 39-41, 1961.

[146] Tarzwell, Robert G., and Basista, David, "Planar Transformers Dissipate Up to 150 kW With Copper Trace Windings," PCIM, vol. 26 no. 3, pp. 58-64, March 2000.

[147] Tarzwell, Robert, "Solving High-Current Design Problems with Ultra-Thick Copper," US-Tech Interactive, February 1998. (download from

[148] Williams, Lisa, "Re: current vs trace width graphs," DesignerCouncil archive #1602, 17 Sep 1997. (download from

[149] Won, "Re: [SI-LIST] Current flow limit for wire bonding," SI-List, October 4, 2000.

I would like to thank Jonathan Fasig for contributing to this bibliography.

Please send critiques, corrections, and/or additions to , or by snailmail to:
John Barnes
216 Hillsboro Ave
Lexington, KY 40511-2105

dBi Corporation was a one-man test house (testing laboratory) based in Lexington, Kentucky, testing a wide variety of commercial electronic products for electromagnetic compatibility (EMC), electromagnetic interference (EMI), and electrostatic discharge (ESD) under its ISO 17025 accreditation. dBi was founded in Winchester, Kentucky in 1995 by Donald R. Bush, shortly after he retired from 30 years service with IBM Lexington's/ Lexmark's EMC Lab. John R. Barnes, who'd worked with Don at IBM Lexington and Lexmark, bought dBi in 2002 after Don's death, and moved the company to Lexington, Kentucky. John closed dBi at 11:59pm EDT on September 30, 2013, because ObamaCrap had increased operating expenses to the point that we could no longer afford to remain in business.

We'd like to thank all of the clients who chose dBi to test their products from 1995 to 2013. Below is a brief summary of our accomplishments during the 18 years we were in business.

From 1995 to 2001, under Don Bush's ownership and operation, dBi:

From 2002 to 2013, under John Barnes' ownership and operation, dBi:

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Last revised December 31, 2010.